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d a t a sh eet preliminary speci?cation supersedes data of 2002 may 22 2003 mar 25 integrated circuits uda1352hl 48 khz iec 60958 audio dac
2003 mar 25 2 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl contents 1 features 1.1 general 1.2 control 1.3 iec 60958 input 1.4 digital sound processing and dac 2 applications 3 general description 4 ordering information 5 quick reference data 6 block diagram 7 pinning 8 functional description 8.1 operating modes 8.2 clock regeneration and lock detection 8.3 crystal oscillator 8.4 mute 8.5 auto mute 8.6 data path 8.7 control 9 l3-bus description 9.1 general 9.2 device addressing 9.3 register addressing 9.4 data write mode 9.5 data read mode 9.6 initialization string 10 i 2 c-bus description 10.1 characteristics of the i 2 c-bus 10.2 bit transfer 10.3 byte transfer 10.4 data transfer 10.5 start and stop conditions 10.6 acknowledgment 10.7 device address 10.8 register address 10.9 write and read data 10.10 write cycle 10.11 read cycle 11 spdif signal format 11.1 spdif channel encoding 11.2 spdif hierarchical layers for audio data 11.3 spdif hierarchical layers for digital data 11.4 timing characteristics 12 register mapping 12.1 clock settings (write) 12.2 i 2 s-bus output settings (write) 12.3 i 2 s-bus input settings (write) 12.4 power-down settings (write) 12.5 volume control left and right (write) 12.6 sound feature mode, treble and bass boost settings (write) 12.7 de-emphasis and mute (write) 12.8 dac source and clock settings (write) 12.9 spdif input settings (write) 12.10 supplemental settings (write) 12.11 pll coarse ratio (write) 12.12 interpolator status (read-out) 12.13 spdif status (read-out) 12.14 channel status (read-out) 12.15 pll status (read-out) 13 limiting values 14 thermal characteristics 15 characteristics 16 timing characteristics 17 application information 18 package outline 19 soldering 19.1 introduction to soldering surface mount packages 19.2 reflow soldering 19.3 wave soldering 19.4 manual soldering 19.5 suitability of surface mount ic packages for wave and reflow soldering methods 20 data sheet status 21 definitions 22 disclaimers 23 purchase of philips i 2 c components
2003 mar 25 3 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 1 features 1.1 general 2.7 to 3.6 v power supply integrated digital filter and digital-to-analog converter (dac) 256f s system clock output 20-bit data path in interpolator high performance no analog post filtering required for dac supported sampling frequencies of 28 up to 55 khz. 1.2 control controlled by either static pins, i 2 c-bus or l3-bus microcontroller interfaces. 1.3 iec 60958 input on-chip amplifier converts iec 60958 input to cmos levels lock status indication at pin lock pulse code modulation (pcm) input signal status indication at pin pcmdet right and left channels each have 40 key channel-status bits available via l3-bus or i 2 c-bus interfaces. 1.4 digital sound processing and dac automatic de-emphasis when using iec 60958 input with audio sample frequencies (f s ) of 32.0, 44.1 and 48.0 khz soft mute using a cosine roll-off circuit selectable via pin mute, l3-bus or i 2 c-bus interfaces left and right independent db linear volume control having 0.25 db steps from 0 to - 50 db, 1 db steps to - 60, - 66 and - db bass boost and treble control in l3-bus or i 2 c-bus modes interpolating filter (f s to 64f s or 128f s ) using cascaded recursive and fir filters fifth-order noise shaper (operating either at 64f s or 128f s ) generates the bitstream for the dac filter stream dac (fsdac). 2 applications digital audio systems. 3 general description the uda1352hl is a single-chip iec 60958 audio decoder with an integrated stereo dac employing bitstream conversion techniques. a lock status signal is available on pin lock, to indicate when the iec 60958 decoder is locked. a pcm detection status signal is available on pin pcmdet to indicate when pcm data is present at the input. by default, the dac output and the data output interface are muted when the decoder is out-of-lock. however, this setting can be overridden in the l3-bus or i 2 c-bus modes. the uda1352hl in package lqfp48 is the full featured version. also available is the uda1352ts in package ssop28 which has the iec 60958 input only to the dac. 4 ordering information type number package name description version uda1352hl lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2
2003 mar 25 4 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 5 quick reference data v ddd =v dda = 3.0 v; iec 60958 input with f s = 48 khz; t amb =25 c; r l =5k w ; all voltages measured with respect to ground; unless otherwise speci?ed. note 1. the output voltage of the dac is proportional to the dac power supply voltage. symbol parameter conditions min. typ. max. unit supplies v ddd digital supply voltage 2.7 3.0 3.6 v v dda analog supply voltage 2.7 3.0 3.6 v i dda(dac) analog supply current of dac power-on - 3.3 - ma power-down; clock off - 35 -m a i dda(pll) analog supply current of pll at f s = 48 khz - 0.5 - ma i ddd(c) digital supply current of core at f s = 48 khz - 9 - ma i ddd digital supply current at f s = 48 khz - 0.6 - ma p 48 power consumption at f s =48khz dac in playback mode - 40 - mw dac in power-down mode - tbf - mw general t rst reset active time - 250 -m s t amb ambient temperature - 40 - +85 c digital-to-analog converter v o(rms) output voltage (rms value) f i = 1.0 khz tone at 0 dbfs; note 1 850 900 950 mv d v o unbalance of output voltages f i = 1.0 khz tone - 0.1 0.4 db (thd+n)/s total harmonic distortion-plus-noise to signal ratio f i = 1.0 khz tone at f s =48khz at 0 dbfs -- 82 - 77 db at - 40 dbfs; a-weighted -- 60 - 52 db s/n 48 signal-to-noise ratio at f s =48khz f i = 1.0 khz tone; code = 0; a-weighted 95 100 - db a cs channel separation f i = 1.0 khz tone - 110 - db
2003 mar 25 5 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 6 block diagram handbook, full pagewidth mgu597 selspdif voutr 1 22 24 reset selclk 21 clock and timing circuit data input interface wsi 9 bcki 8 datai 7 datao 39 wso 40 bcko 36 preem0 userbit 45 31 preem1 33 pcmdet 43 lock 23 n.c. 11, 29, 30, 41, 48 dac voutl 20 dac clkout xtalin 32 oscout 44 xtalout 12 15 v dda(daca) 18 v ssa(daca) 27 v ref 26 test 25 v ssa(daco) 28 v dda(daco) 19 audio feature processor interpolator noise shaper data output interface iec 60958 decoder slicer l3-bus or i 2 c-bus interface non-pcm data sync detector 5 l3data 6 l3clock 10 l3mode 37 da1 42 da0 46 v ddd 3 v ssd 2 v ddd(c) 4 v ssd(c) 35 v dda(pll) 34 v ssa(pll) 16 spdif0 38 47 selstatic seliic 17 spdif1 14 selchan 13 mute uda1352hl fig.1 block diagram.
2003 mar 25 6 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 7 pinning symbol pin type (1) description reset 1 did reset input v ddd(c) 2 ds digital supply voltage for core v ssd 3 dgnd digital ground v ssd(c) 4 dgnd digital ground for core l3data 5 iic l3-bus or i 2 c-bus interface data input and output l3clock 6 dis l3-bus or i 2 c-bus interface clock input datai 7 disd i 2 s-bus data input bcki 8 disd i 2 s-bus bit clock input wsi 9 disd i 2 s-bus word select input l3mode 10 dis l3-bus interface mode input n.c. 11 - not connected xtalout 12 aio crystal oscillator output mute 13 did mute control input selchan 14 did iec 60958 channel selection input xtalin 15 aio crystal oscillator input spdif0 16 aio iec 60958 channel 0 input spdif1 17 aio iec 60958 channel 1 input v dda(daca) 18 as analog supply voltage for dac v dda(daco) 19 as analog supply voltage for dac voutl 20 aio dac left channel analog output selclk 21 did clock source for pll selection input selspdif 22 diu iec 60958 data selection input lock 23 do spdif and pll lock indicator output voutr 24 aio dac right channel analog output test 25 did test pin; must be connected to digital ground (v ssd ) in application v ref 26 aio dac reference voltage v ssa(daca) 27 agnd analog ground for dac v ssa(daco) 28 agnd analog ground for dac n.c. 29 - not connected n.c. 30 - not connected userbit 31 do user data bit output clkout 32 do clock output (256f s ) preem1 33 do iec 60958 input pre-emphasis output 1 v ssa(pll) 34 agnd analog ground for pll v dda(pll) 35 as analog supply voltage for pll bcko 36 do i 2 s-bus bit clock output da1 37 disu a1 device address selection input selstatic 38 diu static pin control selection input datao 3 9 d o i 2 s-bus data output wso 40 do i 2 s-bus word select output
2003 mar 25 7 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl note 1. see table 1. table 1 pin types n.c. 41 - not connected da0 42 disd a0 device address selection input pcmdet 43 do pcm detection indicator output oscout 44 do internal oscillator output preem0 45 do iec 60958 input pre-emphasis output 0 v ddd 46 ds digital supply voltage seliic 47 did i 2 c-bus or l3-bus mode selection input n.c. 48 - not connected type description ds digital supply dgnd digital ground as analog supply agnd analog ground di digital input dis digital schmitt-triggered input did digital input with internal pull-down resistor disd digital schmitt-triggered input with internal pull-down resistor diu digital input with internal pull-up resistor disu digital schmitt-triggered input with internal pull-up resistor do digital output dio digital input and output dios digital schmitt-triggered input and output iic input and open-drain output for i 2 c-bus aio analog input or output symbol pin type (1) description
2003 mar 25 8 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl handbook, full pagewidth uda1352hl mgu596 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 n.c. seliic v ddd preem0 oscout pcmdet da0 n.c. wso datao selstatic da1 mute selchan xtalin spdif0 spdif1 v dda(daca) v dda(daco) voutl selclk selspdif lock voutr reset v ddd(c) v ssd v ssd(c) l3data l3clock datai bcki wsi l3mode n.c. xtalout bcko v dda(pll) v ssa(pll) preem1 clkout userbit n.c. n.c. v ssa(daco) v ssa(daca) v ref test fig.2 pin configuration.
2003 mar 25 9 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 8 functional description 8.1 operating modes the uda1352hl is a low-cost multi-purpose iec 60958 decoder dac with a variety of operating modes. in operating modes 1, 2, 3, 4, 6, 7 and 8, the uda1352hl is the master clock generator for both the outgoing and incoming digital data streams. consequently, any device providing data for the uda1352hl via the data input interface in mode 4 will be a slave to the clock generated by the uda1352hl. in mode 5 the uda1352hl locks to signal wsi from the digital data input interface. to conform to iec 60958, the audio sample frequency of the data input interface must be between 28 and 55 khz. table 2 mode survey mode function schematic 1 iec 60958 input dac output the system locks onto the spdif signal. 2 iec 60958 input i 2 s-bus digital interface output the system locks onto the spdif signal digital output with bcko and wso as master. i 2 s-bus output spdif in dac i 2 s-bus input external dsp mgu598 pll xtal i 2 s-bus output spdif in dac i 2 s-bus input external dsp mgu599 pll xtal
2003 mar 25 10 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 3 iec 60958 input i 2 s-bus digital interface output dac output the system locks onto the spdif signal digital output with bcko and wso as master. 4 iec 60958 input i 2 s-bus digital interface output i 2 s-bus digital interface input dac output the system locks onto the spdif signal digital output with bcko and wso as master digital input with bcki and wsi as slave (must be synchronized with the pll output clock). 5i 2 s-bus digital interface input dac output the system locks onto the wsi signal digital input with bcki and wsi as slave. mode function schematic i 2 s-bus output spdif in dac i 2 s-bus input external dsp mgu600 pll xtal i 2 s-bus output spdif in dac i 2 s-bus input external dsp mgu601 pll xtal i 2 s-bus output spdif in dac i 2 s-bus input external dsp mgu602 pll xtal
2003 mar 25 11 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 6i 2 s-bus digital interface input dac output the crystal oscillator generates the system clock and master clock output digital input with bcki and wsi as slave. 7 iec 60958 input i 2 s-bus digital interface output i 2 s-bus digital interface input dac output spdif input to digital interface output locks onto the spdif signal dac locks onto the crystal oscillator digital output with bcko and wso as master digital input with bcki and wsi as slave (must be synchronized with the pll output clock). 8 crystal oscillator output applied to iec 60958 input i 2 s-bus digital interface output the crystal oscillator generates the master clock pll regenerates bcko and wso from input clock by setting the pre-scaler ratio digital output with bcko and wso as master (invalid data) digital input with bcki and wsi as slave. mode function schematic i 2 s-bus output spdif in dac i 2 s-bus input external dsp mgu603 pll xtal i 2 s-bus output spdif in dac i 2 s-bus input external dsp mgu604 pll xtal i 2 s-bus output spdif in dac i 2 s-bus input mgu605 pll xtal
2003 mar 25 12 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 8.2 clock regeneration and lock detection the uda1352hl has an on-board pll for regenerating a system clock from the iec 60958 input bitstream. remark: if there is no input signal, the pll generates a minimum frequency and the output spectrum shifts accordingly. since the analog output does not have an analog mute, this means noise that is out of band under normal conditions can move into the audio band. when the on-board clock locks to the incoming frequency, the pll lock indicator bit is set and can be read via the l3-bus or i 2 c-bus interfaces. by default, pll lock status and pcm detection status indicator signals are internally combined. pin lock goes high when the iec 60958 decoder and the on-board clock are both locked to the incoming bitstream and if the incoming bitstream data is pcm. however, if the ic is locked but the incoming signal is not pcm data, or it is burst preamble, pin lock goes low. the combined lock and pcm detection status can be overridden by the l3-bus or i 2 c-bus register bit settings. the lock indication output signal can be used, for example, for muting purposes. it can be used to drive an external analog muting circuit to prevent out of band noise from becoming audible when the pll runs at its minimum frequency (e.g. when there is no spdif input signal). when valid pcm data is detected in the incoming bitstream, pin pcmdet goes high. 8.3 crystal oscillator the uda1352hl uses an on-board crystal oscillator to generate a clock signal. the clock signal can be used as the internal clock, and is used directly by the dac in modes 6 and 7. this clock signal can also be output at pin oscout and can be applied to the spdif inputs. by setting the uda1352hl as a frequency synthesizer (mode 8), a set of frequencies can be obtained, as shown in table 53. 8.4 mute the uda1352hl uses a cosine roll-off mute in the dsp data path part of the dac. muting the dac (by pin mute or via bit mt in l3-bus or i 2 c-bus modes), results in a soft mute, as shown in fig.3. the cosine roll-off soft mute takes 23 ms corresponding to 32 32 samples at a sampling frequency of 44.1 khz. when operating in either the l3-bus or i 2 c-bus mode, the device will mute the audio output on start-up by default. muting in these modes can only be disabled by setting bit mt in the device register to logic 0. a logic 1 on pin mute will always mute the audio output signal in either the l3-bus or i 2 c-bus mode, or static pin mode. this is in contrast to the uda1350 and the uda1351 in which pin mute has no effect in the l3-bus mode. handbook, halfpage 010 51525 1 0 0.8 mgu119 20 0.6 0.4 0.2 t (ms) mute factor fig.3 mute as a function of raised cosine roll-off.
2003 mar 25 13 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 8.5 auto mute by default, the dac outputs are muted until the uda1352hl is locked, regardless of the level on pin mute or the state of bit mt. this allows only valid data to be passed to the outputs. this mute is performed in the spdif interface and is a hard mute, not a cosine roll-off mute. the uda1352hl can be prevented from muting in out-of-lock situations by setting bit mutebp in register address 01h to logic 1 via the l3-bus or i 2 c-bus interfaces. 8.6 data path the uda1352hl data path consists of the iec 60958 decoder, audio feature processor, digital interpolator, noise shaper and the dacs. 8.6.1 iec 60958 input the iec 60958 decoder features an on-chip amplifier with hysteresis, which amplifies the spdif input signal to cmos level (see fig.4). all 24 bits of data for left and right channels are extracted from the input bitstream plus 40 channel-status bits for left and right channels. these bits can be read via the l3-bus or i 2 c-bus interfaces. the uda1352hl supports the following sample frequencies and data rates: f s = 32.0 khz, resulting in a data rate of 2.048 mbits/s f s = 44.1 khz, resulting in a data rate of 2.8224 mbits/s f s = 48.0 khz, resulting in a data rate of 3.072 mbits/s. the uda1352hl supports timing levels i, ii and iii, as specified by the iec 60958 standard. the accuracy of the above sampling frequencies depends on the timing levels used. timing levels i, ii and iii are described in section 11.4.1. 8.6.2 a udio feature processor the audio feature processor automatically provides de-emphasis for the iec 60958 data stream in the static pin control mode and default mute at start-up in either the l3-bus or i 2 c-bus mode. when used in l3-bus or i 2 c-bus modes, the audio feature processor provides the following additional features: independent left and right channel volume control bass boost control treble control selection of sound processing modes for bass boost and treble filters: flat, minimum and maximum soft mute control with raised cosine roll-off de-emphasis of the incoming data stream selectable at a sampling frequency of either 32.0, 44.1 or 48.0 khz. handbook, halfpage mgu611 16, 17 spdif0, spdif1 75 w 180 pf 10 nf uda1352hl fig.4 iec 60958 input circuit and typical application.
2003 mar 25 14 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 8.6.3 i nterpolator the uda1352hl has an on-board interpolating filter that converts the incoming data stream from 1f s to 64f s or 128f s by cascading a recursive filter and a finite impulse response (fir) filter. table 3 interpolator characteristics 8.6.4 n oise shaper the fifth-order noise shaper operates either at 64f s or 128f s . it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. the noise shaper output is converted to an analog signal using a filter stream dac. 8.6.5 f ilter stream dac the filter stream dac (fsdac) is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way, very high signal-to-noise performance and low clock jitter sensitivity is achieved. a post filter is not needed due to the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage signal capable of driving a line output. the output voltage of the fsdac is scaled proportionally to the power supply voltage. 8.7 control the uda1352hl can be controlled by static pins (when pin selstatic is high), via the i 2 c-bus (when pin selstatic is low and pin seliic is high) or via the l3-bus (when pins selstatic and seliic are both low). for optimum use of the uda1352hl features, the l3-bus or i 2 c-bus modes are recommended since only basic functions are available in the static pin control mode. note that the static pin control mode and l3-bus or i 2 c-bus modes are mutually exclusive. in the static pin control mode, pins l3mode and l3data are used to select the format for the data output and input interface (see fig.5). parameter conditions value (db) pass-band ripple 0 to 0.45f s 0.03 stop band >0.55f s - 50 dynamic range 0 to 0.45f s 114 dc gain -- 5.67
2003 mar 25 15 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mgs752 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24 bits ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20 bits ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb 16 msb b2 left lsb-justified format 16 bits ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb msb msb b2 2 1 > = 8 12 3 left i 2 s-bus format ws bck data right 3 > = 8 msb b2 fig.5 digital data interface formats.
2003 mar 25 16 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 8.7.1 s tatic pin control mode the functions of the static pins in static pin control mode are described in table 4. table 4 pin descriptions in static pin control mode pin name value function mode selection pin 38 selstatic 1 select static pin control mode; must be connected to v ddd input pins 1 reset 0 normal operation 1 reset 6 l3clock 0 must be connected to v ssd 10 and 5 l3mode and l3data 00 select i 2 s-bus format for digital data interface 01 select lsb-justi?ed format 16 bits for digital data interface 10 select lsb-justi?ed format 20 bits for digital data interface 11 select lsb-justi?ed format 24 bits for digital data interface 13 mute 0 no mute 1 mute active 14 selchan 0 select input spdif 0 (channel 0) 1 select input spdif 1 (channel 1) 21 selclk 0 slave to f s from iec 60958; master on data output and input interfaces 1 slave to f s from digital data input interface 22 selspdif 0 select data from digital data interface to dac output 1 select data from iec 60958 decoder to dac output status pins 43 pcmdet 0 non-pcm data or burst preamble detected 1 pcm data detected 23 lock 0 clock regeneration and iec 60958 decoder out-of-lock or non-pcm data detected 1 clock regeneration and iec 60958 decoder locked and pcm data detected 33 and 45 preem1 and preem0 00 iec 60958 input; no pre-emphasis 01 iec 60958 input; f s = 32.0 khz with pre-emphasis 10 iec 60958 input; f s = 44.1 khz with pre-emphasis 11 iec 60958 input; f s = 48.0 khz with pre-emphasis test pin 25 test 0 must be connected to v ssd
2003 mar 25 17 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 8.7.2 l3- bus or i 2 c- bus modes the l3-bus or i 2 c-bus modes allow maximum flexibility for controlling the uda1352hl. the default values for all non pin-controlled settings are identical to the default values at start-up in the l3-bus or i 2 c-bus modes. the default values are given in section 12. it should be noted that in either l3-bus or i 2 c-bus mode, several base-line functions are still controlled by static pins (see table 5). however, in l3-bus or i 2 c-bus modes, on start-up, the output is muted only by bit mt in register address 13h via the l3-bus or i 2 c-bus interfaces. table 5 pin descriptions in l3-bus or i 2 c-bus modes pin name value function mode selection pins 38 selstatic 0 select l3-bus mode or i 2 c-bus mode; must be connected to v ssd 47 seliic 0 select l3-bus mode; must be connected to v ssd 1 select i 2 c-bus mode; must be connected to v ddd input pins 1 reset 0 normal operation 1 reset 5 l3data - must be connected to the l3-bus - must be connected to the sda line of the i 2 c-bus 6 l3clock - must be connected to the l3-bus - must be connected to the scl line of the i 2 c-bus 10 l3mode - must be connected to the l3-bus 13 mute 0 no mute 1 mute active status pins 43 pcmdet 0 non-pcm data or burst preamble detected 1 pcm data detected 23 lock 0 clock regeneration and iec 60958 decoder out-of-lock or non-pcm data detected 1 clock regeneration and iec 60958 decoder locked and pcm data detected 33 and 45 preem1 and preem0 00 iec 60958 input; no pre-emphasis 01 iec 60958 input; f s = 32.0 khz with pre-emphasis 10 iec 60958 input; f s = 44.1 khz with pre-emphasis 11 iec 60958 input; f s = 48.0 khz with pre-emphasis test pins 25 test 0 must be connected to v ssd
2003 mar 25 18 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 9 l3-bus description 9.1 general the uda1352hl has an l3-bus microcontroller interface allowing all the digital sound processing features and various system settings to be controlled by a microcontroller. the controllable settings are: restoring of l3-bus default values power-on selection of filter mode, and settings for treble and bass boost volume settings for left and right channels selection of soft mute via cosine roll-off and bypass of auto mute selection of de-emphasis (mode 4 to mode 8 only). the readable settings are: mute status of interpolator pll locked spdif input signal locked audio sample frequency valid pcm data detected pre-emphasis of the iec 60958 input signal clock accuracy. the exchange of data and control information between the microcontroller and the uda1352hl is lsb first and is accomplished through the serial hardware l3-bus interface comprising the following pins: l3data: data line l3mode: mode line l3clock: clock line. the l3-bus format has two modes of operation: address mode data transfer mode. the address mode is used to select a device for a subsequent data transfer. the address mode is characterized by l3mode being low and a burst of 8 pulses on l3clock, accompanied by 8 bits (see fig.6). the data transfer mode is characterized by l3mode being high and is used to transfer one or more bytes representing a register address, instruction or data. there are two types of data transfers: write action: data transfer to the device read action: data transfer from the device. remark: when the device is powered-up, the l3-bus interface must receive at least one l3clock pulse before data can be sent to the device (see fig.6). this is only required once after the device is powered-up. 9.2 device addressing the device address is one byte comprising: data operating mode (dom) bits 0 and 1 specifying the type of data transfer (see table 6) address bits 2 to 7 specifying a 6-bit device address. bits 2 and 3 of the address are selected via external pins da0 and da1, allowing up to four uda1352hl devices to be independently controlled in a single application. the primary address of the uda1352hl is 001000 (lsb to msb) and the default address is 011000. table 6 selection of data transfer 9.3 register addressing the device register address is one byte comprising: bit 0 specifying that data is to be either read or written address bits 1 to 7 specifying the 7-bit register address. there are three types of register addressing: to write data: bit 0 is logic 0 specifying that data will be written to the device register, followed by bits 1 to 7 specifying the device register address (see fig.6) to prepare read: bit 0 is logic 1, specifying that data will be read from the device register (see fig.7) to read data: the device returns the device register address prior to sending data from that register. when bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid. dom transfer bit 0 bit 1 0 0 not used 1 0 not used 0 1 write data or prepare read 1 1 read data
2003 mar 25 19 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... mgs753 l3clock l3mode l3data 0 write l3 wake-up pulse after power-up device address dom bits register address data byte 1 data byte 2 10 fig.6 data write mode (for l3-bus version 2). mbl565 l3clock l3mode l3data 0 read valid/invalid device address prepare read sent by the device dom bits register address device address requesting register address data byte 1 data byte 2 111 0/1 1 fig.7 data read mode.
2003 mar 25 20 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 9.4 data write mode the data write mode is explained in the signal diagram of fig.6. to write data to a device requires four bytes to be sent (see table 7): 1. one byte starting with 01 specifying a write action, followed by the device address (011000 for the uda1352hl default) 2. one byte starting with 0 specifying a write action, followed by seven bits specifying the device register address in binary format, with a6 being the msb and a0 being the lsb 3. first of two data bytes with d15 being the msb 4. second of two data bytes with d0 being the lsb. note that to write data to a different register within the same device requires the device address to be sent again. 9.5 data read mode the data read mode is explained in the signal diagram of fig.7. to read data from a device requires a prepare read followed by a data read. six bytes are used, (see table 8): 1. one byte starting with 01 specifying a prepare read action to the device, followed by the device address 2. one byte starting with 1 specifying a read action, followed by seven bits specifying the device register address from which data needs to be read, followed by seven bits specifying the source register address in binary format, with a6 being the msb and a0 being the lsb 3. one byte starting with 11 instructing the device to write data to the microcontroller, followed by the device address 4. one byte, sent by the device to the bus, starting with either a logic 0 to indicate that the requesting register is valid, or a logic 1 to indicate that the requesting register is invalid, followed by the requesting register address 5. first of two data bytes, sent by the device to the bus, with d15 being the msb 6. second of two bytes, sent by the device to the bus, with d0 being the lsb. table 7 l3-bus write data table 8 l3-bus read data byte l3-bus mode action first in time last in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address device address 0 1 da0 da1 1000 2 data transfer register address 0 a6 a5 a4 a3 a2 a1 a0 3 data transfer data byte 1 d15 d14 d13 d12 d11 d10 d9 d8 4 data transfer data byte 2 d7 d6 d5 d4 d3 d2 d1 d0 byte l3-bus mode action first in time last in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address device address 0 1 da0 da1 1000 2 data transfer register address 1 a6 a5 a4 a3 a2 a1 a0 3 address device address 1 1 da0 da1 1000 4 data transfer requesting register address 0 or 1 a6 a5 a4 a3 a2 a1 a0 5 data transfer data byte 1 d15 d14 d13 d12 d11 d10 d9 d8 6 data transfer data byte 2 d7 d6 d5 d4 d3 d2 d1 d0
2003 mar 25 21 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 9.6 initialization string for correct and reliable operation, the uda1352hl must be initialized in the l3-bus mode. this is required to ensure that the pll always starts up, under all conditions, after the device is powered up. the initialization string is given in table 9. table 9 l3-bus initialization string and set defaults after power-up 10 i 2 c-bus description 10.1 characteristics of the i 2 c-bus the i 2 c-bus allows 2-way, 2-line communication between different ics or modules, using a serial data line (sda) and a serial clock line (scl). both lines must be connected to the v dd via a pull-up resistor when connected to the output stages of a microcontroller. for a 400 khz ic you must follow philips semiconductors recommendations for this type of bus, (e.g. a pull-up resistor can be used for loads on the bus of up to 200 pf, and a current source or switched resistor must be used for loads from 200 to 400 pf). data transfer can only be initiated when the bus is not busy. 10.2 bit transfer one data bit is transferred during each clock pulse (see fig.8). the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. the maximum clock frequency is 400 khz. to run at this frequency requires all inputs and outputs connected to this high-speed i 2 c-bus to be designed according to specification the i 2 c-bus and how to use it , (order code 9398 393 40011). byte l3-bus mode action first in time last in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address initialization string device address 0 1 da0 da1 1000 2 data transfer register address 01000000 3 data transfer data byte 1 00000000 4 data transfer data byte 2 00000001 5 address set defaults device address 0 1 da0 da1 1000 6 data transfer register address 01111111 7 data transfer data byte 1 00000000 8 data transfer data byte 2 00000000 handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl fig.8 bit transfer on the i 2 c-bus.
2003 mar 25 22 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 10.3 byte transfer each byte (8 bits) is transferred with the msb first (see table 10). table 10 byte transfer 10.4 data transfer a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. 10.5 start and stop conditions both data and clock lines will remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high, is defined as a start condition (s); see fig.9. a low-to-high transition of the data line while the clock is high is defined as a stop condition (p). msb bit number lsb 76543210 handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.9 start and stop conditions on the i 2 c-bus. 10.6 acknowledgment there is no limit to the number of data bits transferred from the transmitter to receiver between the start and stop conditions. each byte of eight bits is followed by one acknowledge bit (see fig.10). at the acknowledge bit, the data line is released by the master and the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after receiving each byte. also a master must generate an acknowledge after receiving each byte that has been clocked out of the slave transmitter. the acknowledging device must pull-down the sda line during the high period of the acknowledge clock pulse so that the sda line is stable low. set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition.
2003 mar 25 23 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master fig.10 acknowledge on the i 2 c-bus. 10.7 device address before any data is transmitted on the i 2 c-bus, the target device is always addressed first after the start procedure. the target device is addressed using one byte having one of four addresses set by pins da0 and da1. the uda1352hl acts as a slave receiver or a slave transmitter. therefore, the clock signal scl is only an input signal and the data signal sda is bidirectional. the uda1352hl device address is shown in table 11. table 11 i 2 c-bus device address 10.8 register address the register addresses in the i 2 c-bus mode are the same as those in the l3-bus mode. 10.9 write and read data the i 2 c-bus configuration for a write and read cycle are shown in tables 12 and 13, respectively. the write cycle writes pairs of bytes to the internal registers for the digital sound feature control and system setting. these register locations can also be read for device status information. device address r/ w a6 a5 a4 a3 a2 a1 a0 - 1 0 0 1 1 da1 da0 0/1
2003 mar 25 24 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 10.10 write cycle the write cycle is used to write data to the internal registers. the device and register addresses are one byte each, the setting data is always two bytes . the i 2 c-bus configuration for a write cycle is shown in table 12. the write cycle format is as follows: 1. the microcontroller begins by asserting a start condition (s). 2. the first byte (8 bits) contains the device address 1001 110 and the r/ w bit is set to logic 0 (write). 3. the uda1352hl asserts an acknowledge (a). 4. the microcontroller writes the 8-bit address (addr) of the uda1352hl register to which data will be written. 5. the uda1352hl acknowledges (a) this register address. 6. the microcontroller sends two bytes of data with the most significant (ms) byte first followed by the least significant (ls) byte; after each byte th e uda1352hl asserts an acknowledge. 7. after every pair of bytes that are transmitted, the register address is auto incremented; after each byte the uda1352hl asser ts an acknowledge. 8. the uda1352hl frees the i 2 c-bus allowing the microcontroller to generate a stop condition (p). table 12 master transmitter writes to the uda1352hl registers in i 2 c-bus mode. note 1. auto increment of register address. device address r/ w register address data 1 data 2 (1) data n (1) s 1001 110 0 a addr a ms1 a ls1 a ms2 a ls2 a msn a lsn a p acknowledge from uda1352hl
2003 mar 25 25 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 10.11 read cycle the read cycle is used to read the data values from the internal registers. the i 2 c-bus configuration for a read cycle is shown in table 13. the read cycle format is as follows: 1. the microcontroller begins by asserting a start condition (s). 2. the first byte (8 bits) contains the device address 1001 110 and the r/ w bit is set to logic 0 (write). 3. the uda1352hl asserts an acknowledge (a). 4. the microcontroller writes the 8-bit address (addr) of the uda1352hl register from which data will be read. 5. the uda1352hl acknowledges (a) this register address. 6. the microcontroller generates a repeated start (sr). 7. the microcontroller generates the device address 1001 110 again, but this time the r/ w bit is set to logic 1 (read). 8. the uda1352hl asserts an acknowledge (a). 9. the uda1352hl sends two bytes of data with the most significant (ms) byte first followed by the least significant (ls) byte; after each byte the microcontroller asserts an acknowledge. 10. after every pair of bytes that are transmitted, the register address is auto incremented; after each byte the microcontroller asserts an acknowle dge. 11. the microcontroller stops this cycle by generating a negative acknowledge (na). 12. the uda1352hl frees the i 2 c-bus allowing the microcontroller to generate a stop condition (p). table 13 master transmitter reads the uda1352hl registers in i 2 c-bus mode. note 1. auto increment of register address. device address r/ w register address device address r/ w data 1 data 2 (1) data n (1) s 1001 110 0 a addr a sr 1001 110 1 a ms1 a ls1 a ms2 a ls2 a msn a lsn na p acknowledge from uda1352hl acknowledge from master
2003 mar 25 26 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 11 spdif signal format 11.1 spdif channel encoding the digital signal is coded using bi-phase mark code (bmc) which is a type of phase-modulation. in this scheme, a logic 1 in the data corresponds to two zero-crossings in the coded signal, and a logic 0 corresponds to one zero-crossing. an example of the encoding is given in fig.11. from an abstract point of view, an spdif signal can be represented as shown in fig.12. audio or digital data is transmitted in sequential blocks. each block comprises 192 frames. each frame contains two sub-frames. each sub-frame is preceded by a preamble word, of which there are three types: b, m and w. preamble b signifies the start of channel 1 at the start of a data block, m signifies the start of channel 1 that is not at the start of a data block, and w signifies the start of channel 2. each of these preamble words can have one of two values depending on the value of the parity bit in the previous frame. preambles are easily identifiable because these sequences can never occur in the channel parts of a valid spdif stream, see table 14. the spdif signal format used for audio data (pcm mode) and digital data (non-pcm mode) are different. however, both formats have a validity bit that indicates whether the sample is valid, a user data bit, a channel status bit, and a parity bit in each sub-frame. 11.2 spdif hierarchical layers for audio data a two-channel pcm signal uses one sub-frame per channel. each sub-frame contains a single 20-bit audio sample which can extend to 24 bits (see fig.13). data bits 4 to 31 in each sub-frame are modulated using a bmc scheme. sync preamble bits 0 to 3 contain a violation of the bmc scheme to allow them to be easily identified. table 14 preamble values 11.3 spdif hierarchical layers for digital data for transmitting non-pcm data, the iec 60958 protocol allocates the time slot bits shown in table 15 to each sub-frame. table 15 bit allocation of digital data as shown in table 15 and fig.14, the non-pcm encoded data occurs within the 16-bit data stream area of the iec 60958 sub-frame in time-slots 12 (lsb) to 27 (msb). handbook, halfpage data clock bmc mgu606 fig.11 bi-phase mark encoding. preceding parity bit value preamble word bmw 0 1110 1000 1110 0010 1110 0100 1 0001 0111 0001 1101 0001 1011 field iec 60958 time slot bits description 0 to 3 preamble iec 60958 preamble 4 to 7 auxiliary bits not used; all logic 0 8 to 11 unused data bits not used; all logic 0 12 to 27 part of 16-bit data part of the digital bitstream 28 validity bit according to iec 60958 29 user data bit according to iec 60958 30 channel status bit according to iec 60958 31 parity bit according to iec 60958
2003 mar 25 27 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl handbook, full pagewidth channel 1 mmm ww w b channel 2 channel 1 sub-frame channel 2 channel 1 channel 2 channel 1 channel 2 frame 0 frame 191 frame 191 block mgu607 sub-frame fig.12 spdif block format. handbook, full pagewidth sync preamble auxiliary 03478 27 28 31 l s b l s b m s b p audio sample word c u v validity flag user data channel status parity bit mgu608 fig.13 sub-frame format in pcm mode. handbook, full pagewidth sync preamble auxiliary 03478 27 28 31 l s b l s b 11 12 l s b m s b p 16-bit data stream unused data c u v validity flag user data channel status parity bit mgu609 fig.14 sub-frame format in non-pcm mode.
2003 mar 25 28 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 11.3.1 b itstream format the non-pcm data is transmitted in time-slots 12 to 27 as data bursts comprising four 16-bit preamble words (called pa, pb, pc and pd) followed by the so-called burst-payload. the burst preamble words are defined in table 16. table 16 burst preamble words 11.3.2 b urst information the burst information in preamble pc is defined according to iec 60958. the preamble pc fields are described in table 17. table 17 burst information ?elds in preamble pc preamble word length of the field contents value pa 16 bits sync word 1 f872h pb 16 bits sync word 2 4e1fh pc 16 bits burst information see table 17 pd 16 bits length code number of bits pc bits value content reference point r data burst repetition period (iec 60958 frames) 0 to 4 0 null data - none 1 ac-3 data r_ac-3 1536 2 reserved -- 3 pause bit 0 of pa refer to iec 60958 4 mpeg-1 layer 1 data bit 0 of pa 384 5 mpeg-1 layer 1, 2 or 3 data or mpeg-2 without extension bit 0 of pa 1152 6 mpeg-2 with extension bit 0 of pa 1152 7 reserved -- 8 mpeg-2, layer 1 low sampling rate bit 0 of pa 768 9 mpeg-2, layer 2 or 3 low sampling rate bit 0 of pa 2304 10 reserved -- 11 to 13 reserved (dts) - refer to iec 61937 14 to 31 reserved -- 5 to 6 0 reserved -- 7 0 error ?ag indicating a valid burst-payload -- 1 error ?ag indicating an invalid burst-payload -- 8to12 - data type dependant information -- 13 to 15 0 bitstream number --
2003 mar 25 29 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 11.3.3 m inimum burst spacing a data burst is defined as not exceeding 4096 frames, followed by a synchronisation sequence of 96 bits comprising two frames, and four sub-frames, each containing 16 zeroes, followed by burst preamble words pa and pb. this synchronisation sequence allows the start of a new burst-payload to be detected including burst preamble words pc and pd that contain additional bitstream information. 11.3.4 u ser data bit the data that is present in the user data bit in each sub-frame is available as a bitstream output at pin userbit. the userbit output data is synchronized with the i 2 s-bus word select output at pin wso (see fig.15). handbook, full pagewidth channel 1 channel 2 channel 2 channel 1 channel 2 channel 2 channel 1 channel 2 channel 2 wso (i 2 s-bus format) wso (other formats) userbit mgu610 fig.15 userbit output timing.
2003 mar 25 30 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 11.4 timing characteristics 11.4.1 f requency requirements the spdif specification iec 60958 supports the following three levels of clock accuracy: level i: high accuracy; requires the transmitted sampling frequency to have a tolerance of within 50 10 - 6 level ii: normal accuracy; requires all receivers to have an input sampling frequency of within 1000 10 - 6 of the nominal sampling frequency level iii: variable pitch shifted clock mode; allows a sampling frequency deviation of 12.5% of the nominal sampling frequency. 11.4.2 r ise and fall times rise and fall times (see fig.16) are defined as: rise time = fall time = rise and fall times should be in the range: 0% to 20% when the data bit is a logic 1 0% to 10% when two consecutive data bits are both logic 0. 11.4.3 d uty cycle the duty cycle (see fig.16) is defined as: duty cycle = the duty cycle should be in the range: 40% to 60% when the data bit is a logic 1 45% to 55% when two consecutive data bits are both logic 0. t r t l t h + () -------------------- 100% t f t l t h + () -------------------- 100% t h t l t h + () -------------------- 100% handbook, halfpage 90% t h 50% 10% mgu612 t r t f t l fig.16 rise and fall times.
2003 mar 25 31 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12 register mapping table 18 register map of control settings (write) table 19 register map of status bits (read-out) register address function system settings 00h clock settings 01h i 2 s-bus output settings 02h i 2 s-bus input settings 03h power-down settings interpolator 10h volume control left and right 12h sound feature mode, treble and bass boost 13h de-emphasis and mute 14h dac source and clock settings spdif input settings 30h spdif input settings supplemental settings 40h supplemental settings pll settings 62h pll coarse ratio software reset 7fh restore l3-bus default values register address function interpolator 18h interpolator status spdif input 59h spdif status 5ah channel status bits left [15:0] 5bh channel status bits left [31:16] 5ch channel status bits left [39:32] 5dh channel status bits right [15:0] 5eh channel status bits right [31:16] 5fh channel status bits right [39:32] pll 68h pll status
2003 mar 25 32 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.1 clock settings (write) table 20 register address 00h table 21 description of register bits note 1. these bits cannot be read. table 22 crystal clock divider ratio settings bit 15 14 13 12 11 10 9 8 symbol ------ xtal_div1 xtal_div0 default ------ 00 bit76543210 symbol ---- xratio1 xratio0 clkout_ sel freq_ synth0 default ---- 0000 bit symbol description 15 to 10 - reserved 9 to 8 xtal_div[1:0] crystal clock divider ratio settings. a 2-bit value to set the division ratio between the internal crystal oscillator frequency and the dac sampling frequency in crystal operation mode (dac clock is ?xed at 64f s ). default value is 00; note 1. see table 22 for alternative values. 7to4 - reserved 3 to 2 xratio[1:0] pre-scaler ratio settings. a 2-bit value to set the pre-scaler ratio in frequency synthesizer mode (freq_synth0 is logic 1). default value is 00, see table 23. 1 clkout_sel clock output select. a 1-bit value. when set to logic 1, the internal crystal oscillator signal is used as the clock signal and is also available from pin clkout. when set to logic 0, the clock signal is recovered from the spdif or wsi input signal. default value is logic 0. 0 freq_synth0 frequency synthesizer mode. a 1-bit value. when set to logic 1, frequency synthesizer mode is enabled. when set to logic 0, the frequency synthesizer mode is disabled. default value is logic 0. xtal_div1 xtal_div0 crystal clock and ratio 0 0 128f s ; ratio 1:2 (default) 0 1 256f s ; ratio 1:4 1 0 384f s ; ratio 1:6 1 1 512f s ; ratio 1:8
2003 mar 25 33 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl table 23 pre-scaler ratio settings 12.2 i 2 s-bus output settings (write) table 24 register address 01h table 25 description of register bits table 26 digital data output formats xratio1 xratio0 pre-scaler ratio 0 0 1:36 (default) 0 1 1:625 1 0 1:640 1 1 1:1125 bit 15 14 13 12 11 10 9 8 symbol ------- mutebp default ------- 0 bit 7 6 5 4 3 2 1 0 symbol ----- sforo2 sforo1 sforo0 default ----- 00 0 bit symbol description 15 to 9 - reserved 8 mutebp mute bypass setting. a 1-bit value. when set to logic 1, the mute bypass setting is enabled; in out-of-lock situations or when non-pcm data is detected, the output data is not muted. when set to logic 0, the output is muted in out-of-lock situations. default value is logic 0. 7to3 - reserved 2 to 0 sforo[2:0] digital data output formats. a 3-bit value to set the digital output format. default value 000; see table 26. sforo2 sforo1 sforo0 format 000i 2 s-bus (default) 0 0 1 lsb-justi?ed, 16 bits 0 1 0 lsb-justi?ed, 18 bits 0 1 1 lsb-justi?ed, 20 bits 1 0 0 lsb-justi?ed, 24 bits 1 0 1 msb-justi?ed 1 1 0 reserved 111
2003 mar 25 34 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.3 i 2 s-bus input settings (write) table 27 register address 02h table 28 description of register bits table 29 digital data input formats bit 15 14 13 12 11 10 9 8 symbol - ------- default - ------- bit7 6543210 symbol ----- sfori2 sfori1 sfori0 default ----- 000 bit symbol description 15 to 3 - reserved 2 to 0 sfori[2:0] digital data input formats. a 3-bit value to set the digital input format. default value 000; see table 29. sfori2 sfori1 sfori0 format 000i 2 s-bus (default) 0 0 1 lsb-justi?ed, 16 bits 0 1 0 lsb-justi?ed, 18 bits 0 1 1 lsb-justi?ed, 20 bits 1 0 0 lsb-justi?ed, 24 bits 1 0 1 msb-justi?ed 1 1 0 reserved 111
2003 mar 25 35 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.4 power-down settings (write) table 30 register address 03h table 31 description of register bits bit 15 14 13 12 11 10 9 8 symbol --- pon_xtal ---- default --- 0 ---- bit76543210 symbol --- pon_ spdifin -- en_int pondac default --- 1 -- 11 bit symbol description 15 to 13 - reserved 12 pon_xtal crystal oscillator operation. a 1-bit value. when set to logic 0, the crystal oscillator is disabled. when set to logic 1, the crystal oscillator is enabled. default value is logic 0. 11 to 5 - reserved 4 pon_spdifin power control spdif input. a 1-bit value. when logic 0, power to the iec 60958 bit slicer is disabled. when set to logic 1, the power is enabled. default value is logic 1. 3to2 - reserved 1 en_int interpolator clock control. a 1-bit value. when set to logic 0, the interpolator clock is disabled. when set to logic 1, the interpolator clock is enabled. default value is logic 1. 0 pondac power control dac. a 1-bit value to switch the dac into power-on or power-down mode. when set to logic 0, the dac is in power-down mode. when set to logic 1, the dac is in power-on mode. default value is logic 1.
2003 mar 25 36 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.5 volume control left and right (write) table 32 register address 10h table 33 description of register bits table 34 volume settings left and right channel bit 15 14 13 12 11 10 9 8 symbol vcl_7 vcl_6 vcl_5 vcl_4 vcl_3 vcl_2 vcl_1 vcl_0 default 00000000 bit76543210 symbol vcr_7 vcr_6 vcr_5 vcr_4 vcr_3 vcr_2 vcr_1 vcr_0 default 00000000 bit symbol description 15 to 8 vcl_[7:0] volume setting left channel. an 8-bit value to program the left channel volume attenuation. ranges are 0 to - 50 db in steps of 0.25 db, and - 50 to - 60 db in steps of 1 db, followed by - 66 db and - db. default value 0000 0000; see table 34. 7 to 0 vcr_[7:0] volume setting right channel. an 8-bit value to program the right channel volume attenuation. ranges are 0 to - 50 db in steps of 0.25 db, and - 50 to - 60 db in steps of 1 db, followed by - 66 db and - db. default value 0000 0000; see table 34. vcl_7 vcl_6 vcl_5 vcl_4 vcl_3 vcl_2 vcl_1 vcl_0 volume (db) vcr_7 vcr_6 vcr_5 vcr_4 vcr_3 vcr_2 vcr_1 vcr_0 000000000 (default) 00000001 - 0.25 00000010 - 0.5 ::::::::: 11000111 - 49.75 11001000 - 50 11001100 - 51 11010000 - 52 ::::::::: 11110000 - 60 11110100 - 66 11111000 - 11111100 - ::::::::: 11111111 -
2003 mar 25 37 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.6 sound feature mode, treble and bass boost settings (write) table 35 register address 12h table 36 description of register bits table 37 sound feature mode table 38 treble settings bit 15 14 13 12 11 10 9 8 symbol m1 m0 tr1 tr0 bb3 bb2 bb1 bb0 default 00000000 bit76543210 symbol -------- default -------- bit symbol description 15 to 14 m[1:0] sound feature mode. a 2-bit value to program the sound processing filter mode for treble, and bass boost settings. default value 00; see table 37. 13 to 12 tr[1:0] treble settings. a 2-bit value to program the treble setting. the sound processing filter mode is selected by the sound feature mode bits. default value 00; see table 38. 11 to 8 bb[3:0] bass boost settings. a 4-bit value to program the bass boost setting. the sound processing filter mode is selected by the sound feature mode bits. default value 0000; see table 39. 7to0 - reserved m1 m0 mode selection 0 0 ?at set (default) 0 1 minimum set 10 1 1 maximum set tr1 tr0 flat set (db) minimum set (db) maximum set (db) 0 0000 0 1022 1 0044 1 1066
2003 mar 25 38 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl table 39 bass boost settings bb3 bb2 bb1 bb0 flat set (db) minimum set (db) maximum set (db) 0000 0 0 0 0001 0 2 2 0010 0 4 4 0011 0 6 6 0100 0 8 8 0101 0 10 10 0110 0 12 12 0111 0 14 14 1000 0 16 16 1001 0 18 18 1010 0 18 20 1011 0 18 22 1100 0 18 24 1101 0 18 24 1110 0 18 24 1111 0 18 24
2003 mar 25 39 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.7 de-emphasis and mute (write) table 40 register address 13h table 41 description of register bits table 42 de-emphasis select bit 15 14 13 12 11 10 9 8 symbol qmute mt gs -- de_2 de_1 de_0 default 0 1 0 -- 000 bit76543210 symbol -------- default -------- bit symbol description 15 qmute quick mute function. a 1-bit value to set the quick mute mode. when set to logic 0, the soft mute mode is selected. when set to logic 1, the quick mute mode is selected. default value 0. 14 mt mute. a 1-bit value to set the mute function. when set to logic 0, the audio output is not muted (unless pin mute is logic 1). when set to logic 1, the audio output is muted. default value 1. 13 gs gain select. a 1-bit value to set the gain of the interpolator path. when set to logic 0, the gain is 0 db. when set to logic 1, the gain is 6 db. default value 0. 12 to 11 - reserved 10 to 8 de_[2:0] de-emphasis select. a 3-bit value to enable digital de-emphasis. this setting is only effective in operating modes 4 to 8. in modes 1 and 3, de-emphasis is applied automatically. default value 000; see table 42. 7to0 - reserved de_2 de_1 de_0 function 0 0 0 no de-emphasis (default) 0 0 1 32 khz 0 1 0 44.1 khz 0 1 1 48 khz
2003 mar 25 40 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.8 dac source and clock settings (write) table 43 register address 14h table 44 description of register bits table 45 dac input selection bit 15 14 13 12 11 10 9 8 symbol da_pol_ inv audio_fs ---- dac_sel1 dac_sel0 default 0 1 ---- 10 bit76543210 symbol -------- default 0 ------- bit symbol description 15 da_pol_inv dac polarity control. a 1-bit value to control the signal polarity of the dac output signal. when set to logic 0, the dac output is not inverted. when set to logic 1, the dac output is inverted. default value 0. 14 audio_fs sample frequency range selection. a 1-bit value to select the sampling frequency range. when set to logic 0, the frequency range is approximately 8 to 50 khz; the frequency range in modes 6 and 7 is 8 to 28 khz. when set to logic 1, the frequency range is approximately 28 to 55 khz. default value 1. 13 to 10 - reserved 9 to 8 dac_sel[1:0] dac input selection. a 2-bit value to select the data and clock sources for the dac and the input source for the pll. the dac data source is either the iec 60958 input or the digital input interface. default value 10; see table 45. 7to0 - reserved dac_sel1 dac_sel0 dac input dac clock pll input 0 0 input from i 2 s-bus pll spdif 0 1 input from i 2 s-bus pll wsi 1 0 input from iec 60958 pll spdif 1 1 input from i 2 s-bus crystal spdif
2003 mar 25 41 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.9 spdif input settings (write) table 46 register address 30h table 47 description of register bits bit 15 14 13 12 11 10 9 8 symbol -------- default -------- bit76543210 symbol ---- combine_ pcm burst_ det_en - slice_ sel default ---- 1100 bit symbol description 15 to 4 - reserved 3 combine_pcm combine pcm detection to lock indicator. a 1-bit value to combine the pcm detection status with the spdif and pll lock indicator. when set to logic 0, the lock indicator does not include pcm detection status. when set to logic 1, the pcm detection status is combined with the lock indicator. default value 1. 2 burst_ det_en burst preamble settings. a 1-bit value to enable auto mute when burst preambles are detected. when set to logic 0, muting is disabled. when set to logic 1, muting is enabled; the output is muted when preambles are detected. default value 1. 1 - when writing new settings via the l3-bus or i 2 c-bus interfaces, this bit should stay at logic 0 (default value) to guarantee correct operation. 0 slice_sel slicer input selection. a 1-bit value to select an iec 60958 input signal. when set to logic 0, the input signal is from pin spdif0. when set to logic 1, the input signal is from pin spdif1. default value 0.
2003 mar 25 42 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.10 supplemental settings (write) table 48 register address 40h table 49 description of register bits bit 15 14 13 12 11 10 9 8 symbol oscout_ en ---- ev2 -- default 0 0 0 0 0 0 0 0 bit76543210 symbol -------- default 0 0 0 0 0 0 0 0 bit symbol description 15 oscout_en crystal oscillator output control. a 1-bit value to enable the crystal oscillator output from pin oscout when the crystal oscillator is enabled (bit pon_xtal is logic 1 in register address 03h). when set to logic 0, pin oscout is disabled. when bits oscout_en and pon_xtal are both set to logic 1, the crystal oscillator output appears at pin oscout. default value 0. 14 to 11, 9to0 - when writing new settings via the l3-bus or i 2 c-bus interfaces, these bits should stay at logic 0 (default value) to guarantee correct operation. 10 ev2 pll pull-in range selection. a 1-bit value to adjust the pll pull-in range. when in frequency synthesizer mode (mode 8), this bit should be set to logic 1 to guarantee correct operation. default value 0.
2003 mar 25 43 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.11 pll coarse ratio (write) table 50 register address 62h table 51 description of register bits table 52 coarse ratio setting for pll, notes 1 and 2. notes 1. in frequency synthesizer mode (mode 8), combinations of input frequency (f i ), pr and cr as given in table 53 are supported. in all other modes, cr[15:0] must be set to the default value 0300h. 2. in frequency synthesizer mode (mode 8), ev2 (bit 10 in register address 40h) must be set to logic 1. table 53 possible combinations of f i , pre-scaler ratio (pr) and course ratio (cr) bit 15 14 13 12 11 10 9 8 symbol cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 default 0 0 0 0 0 0 1 1 bit76543210 symbol cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 default 0 0 0 0 0 0 0 0 bit symbol description 15 to 0 cr[15:0] coarse ratio setting for pll. a 16-bit value to program the coarse ratio for the pll in mode 8. default setting 0300h; see table 52. cr15 to cr0 coarse ratio - cr15 2 15 + ... + cr15 2 0 f i (khz) pr cr ws frequency (khz) 12000 1/625 320 8000 12000 1/625 441 11025 12000 1/625 882 22050 12000 1/625 1280 32000 12000 1/625 1764 44100 12000 1/625 1920 48000 12288 1/640 320 8000 12288 1/640 441 11025 12288 1/640 882 22050 12288 1/640 1280 32000 12288 1/640 1764 44100 12288 1/640 1920 48000
2003 mar 25 44 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.12 interpolator status (read-out) table 54 register address 18h table 55 description of register bits 12.13 spdif status (read-out) table 56 register address 59h table 57 description of register bits bit 15 14 13 12 11 10 9 8 symbol -------- bit76543210 symbol ----- mute_ s tat e -- bit symbol description 15 to 3 - reserved 2 mute_state mute status bit. a 1-bit value to indicate the status of the mute function. logic 0 indicates the audio output is not muted. logic 1 indicates the mute sequence has been completed and the audio output is muted. 1to0 - reserved bit 15 14 13 12 11 10 9 8 symbol -------- bit76543210 symbol ---- slice_ stat burst_ det b_err spdifin_ lock bit symbol description 15 to 4 - reserved 3 slice_stat slicer source status. a 1-bit value to indicate which spdif input pin is selected for the input source. logic 0 indicates the iec 60958 input is from pin spdif0. logic 1 indicates the iec 60958 input is from pin spdif1. 2 burst_det burst preamble detection. a 1-bit value to indicate whether burst preamble words are detected in the spdif stream or not. logic 0 indicates no preamble words are detected. logic 1 indicates the burst-payload is detected. 1 b_err bit error detection. a 1-bit value to indicate whether there are bit errors detected in the spdif stream or not. logic 0 indicates no errors are detected. logic 1 indicates bi-phase errors are detected. 0 spdifin_lock spdif lock indicator. a 1-bit value to indicate whether the spdif decoder block is in lock or not. logic 0 indicates the decoder block is out-of-lock. logic 1 indicates the decoder block is in lock.
2003 mar 25 45 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.14 channel status (read-out) for details of channel status information, please refer to publication iec 60958 digital audio interface . 12.14.1 c hannel status bits left [15:0] table 58 register address 5ah 12.14.2 c hannel status bits left [31:16] table 59 register address 5bh 12.14.3 c hannel status bits left [39:32] table 60 register address 5ch 12.14.4 c hannel status bits right [15:0] table 61 register address 5dh bit 15 14 13 12 11 10 9 8 symbol spdi_ bit15 spdi_ bit14 spdi_ bit13 spdi_ bit12 spdi_ bit11 spdi_ bit10 spdi_ bit9 spdi_ bit8 bit76543210 symbol spdi_ bit7 spdi_ bit6 spdi_ bit5 spdi_ bit4 spdi_ bit3 spdi_ bit2 spdi_ bit1 spdi_ bit0 bit 15 14 13 12 11 10 9 8 symbol spdi_ bit31 spdi_ bit30 spdi_ bit29 spdi_ bit28 spdi_ bit27 spdi_ bit26 spdi_ bit25 spdi_ bit24 bit76543210 symbol spdi_ bit23 spdi_ bit22 spdi_ bit21 spdi_ bit20 spdi_ bit19 spdi_ bit18 spdi_ bit17 spdi_ bit16 bit 15 14 13 12 11 10 9 8 symbol -------- bit76543210 symbol spdi_ bit39 spdi_ bit38 spdi_ bit37 spdi_ bit36 spdi_ bit35 spdi_ bit34 spdi_ bit33 spdi_ bit32 bit 15 14 13 12 11 10 9 8 symbol spdi_ bit15 spdi_ bit14 spdi_ bit13 spdi_ bit12 spdi_ bit11 spdi_ bit10 spdi_ bit9 spdi_ bit8 bit76543210 symbol spdi_ bit7 spdi_ bit6 spdi_ bit5 spdi_ bit4 spdi_ bit3 spdi_ bit2 spdi_ bit1 spdi_ bit0
2003 mar 25 46 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.14.5 c hannel status bits right [31:16] table 62 register address 5eh 12.14.6 c hannel status bits right [39:32] table 63 register address 5fh table 64 description of register bits (two times 40 bits indicating the left and right channel status) bit 15 14 13 12 11 10 9 8 symbol spdi_ bit31 spdi_ bit30 spdi_ bit29 spdi_ bit28 spdi_ bit27 spdi_ bit26 spdi_ bit25 spdi_ bit24 bit76543210 symbol spdi_ bit23 spdi_ bit22 spdi_ bit21 spdi_ bit20 spdi_ bit19 spdi_ bit18 spdi_ bit17 spdi_ bit16 bit 15 14 13 12 11 10 9 8 symbol -------- bit76543210 symbol spdi_ bit39 spdi_ bit38 spdi_ bit37 spdi_ bit36 spdi_ bit35 spdi_ bit34 spdi_ bit33 spdi_ bit32 bit symbol description 39 to 36 - reserved but currently unde?ned 35 to 33 spdi_bit[35:33] word length. a 3-bit value indicating the word length; see table 65. 32 spdi_bit[32] audio sample word length. a 1-bit value to indicate the maximum audio sample word length. logic 0 indicates the maximum length is 20 bits. logic 1 indicates the maximum length is 24 bits. 31 to 30 spdi_bit[31:30] reserved 29 to 28 spdi_bit[29:28] clock accuracy. a 2-bit value indicating the clock accuracy; see table 66. 27 to 24 spdi_bit[27:24] sampling frequency. a 4-bit value indicating the sampling frequency; see table 67. 23 to 20 spdi_bit[23:20] channel number. a 4-bit value indicating the channel number; see table 68. 19 to 16 spdi_bit[19:16] source number. a 4-bit value indicating the source number; see table 69. 15 to 8 spdi_bit[15:8] general information. an 8-bit value indicating general information; see table 70. 7 to 6 spdi_bit[7:6] mode. a 2-bit value indicating mode 0; see table 71. 5 to 3 spdi_bit[5:3] audio sampling. a 3-bit value indicating the type of audio sampling; see table 72. 2 spdi_bit2 software copyright. a 1-bit value indicating the copyright status of the software. logic 0 indicates copyright is asserted. logic 1 indicates no copyright is asserted. 1 spdi_bit1 audio sample word. a 1-bit value indicating the type of audio sample word. logic 0 indicates the audio sample word represents linear pcm samples. logic 1 indicates the audio sample word is used for other purposes. 0 spdi_bit0 channel status. a 1-bit value indicating consumer use of the status block. this bit is logic 0.
2003 mar 25 47 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl table 65 word length table 66 clock accuracy table 67 sampling frequency spdi_bit35 spdi_bit34 spdi_bit33 word length spdi_bit32 = 0 spdi_bit32 = 1 0 0 0 word length not indicated (default) word length not indicated (default) 0 0 1 16 bits 20 bits 0 1 0 18 bits 22 bits 0 1 1 reserved reserved 1 0 0 19 bits 23 bits 1 0 1 20 bits 24 bits 1 1 0 17 bits 21 bits 1 1 1 reserved reserved spdi_bit29 spdi_bit28 clock accuracy 0 0 level ii 01leveli 1 0 level iii 1 1 reserved spdi_bit27 spdi_bit26 spdi_bit25 spdi_bit24 sampling frequency 0000 44.1 khz 0001 reserved 001048khz 001132khz :::: other states reserved 1111
2003 mar 25 48 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl table 68 channel number table 69 source number spdi_bit23 spdi_bit22 spdi_bit21 spdi_bit20 channel number 0000 dont care 0001a (left for stereo transmission) 0010b(r ight for stereo transmission) 0011c 0100d 0101e 0110f 0111g 1000h 1001i 1010j 1011k 1100l 1101m 1110n 1111o spdi_bit19 spdi_bit18 spdi_bit17 spdi_bit16 source number 0000 dont care 00011 00102 00113 01004 01015 01106 01117 10008 10019 101010 101111 110012 110113 111014 111115
2003 mar 25 49 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl table 70 category code groups note 1. bit-l indicates the generation status of the digital audio signal. for more details, please refer to publication iec 60958 digital audio interface . table 71 mode table 72 audio sampling spdi_bit[15:8] function 000 00000 general lxx xx001 laser optical products; note 1 lxx xx010 digital-to-digital converters and signal processing products lxx xx011 magnetic tape or disc based products lxx xx100 broadcast reception of digitally encoded audio signals with video signals lxx x1110 broadcast reception of digitally encoded audio signals without video signals lxx xx101 musical instruments, microphones and other sources without copyright information lxx 00110 analog-to-digital converters for analog signals without copyright information lxx 10110 analog-to-digital converters for analog signals which include copyright information in the form of cp- and l-bit status lxx x1000 solid state memory based products l10 00000 experimental products not for commercial sale lxx xx111 reserved lxx x0000 reserved, except 000 0000 and l10 00000 spdi_bit7 spdi_bit6 mode 0 0 mode 0 0 1 reserved 10 11 spdi_bit5 spdi_bit4 spdi_bit3 audio sample spdi_bit1 = 0 spdi_bit1 = 1 0 0 0 2 audio samples without pre-emphasis default state for applications other than linear pcm 0 0 1 2 audio samples with 50/15 m s pre-emphasis other states reserved 0 1 0 reserved (2 audio samples with pre-emphasis) 0 1 1 reserved (2 audio samples with pre-emphasis) : : : other states reserved 111
2003 mar 25 50 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 12.15 pll status (read-out) table 73 register address 68h table 74 description of register bits table 75 lock status indicators of the pll bit 15 14 13 12 11 10 9 8 symbol ------- pll_ lock bit76543210 symbol --- vco_ timeout ---- bit symbol description 15 to 9 - reserved 8 pll_lock pll lock. a 1-bit value indicating the pll lock status; used with bit 4 to indicate pll status; see table 75. 7to5 - reserved 4 vco_timeout vco time-out. a 1-bit value indicating the vco time-out status; used with bit 8 to indicate pll status; see table 75. 3to0 - reserved pll_lock vco_timeout function 0 0 pll out-of-lock 0 1 pll time-out 1 0 pll in lock 1 1 pll time-out
2003 mar 25 51 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 13 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. all v dd and v ss connections must be made to the same power supply. 2. jedec class 2 compliant. 3. jedec class b compliant. 4. dac operation after short-circuiting cannot be warranted. 14 thermal characteristics 15 characteristics v ddd =v dda = 3.0 v; iec 60958 input with f s = 48 khz; t amb =25 c; r l =5k w ; all voltages measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage note 1 2.7 5.0 v t xtal crystal temperature - 25 +150 c t stg storage temperature - 65 +125 c t amb ambient temperature - 40 +85 c v esd electrostatic discharge voltage human body model (hbm); note 2 - 2000 +2000 v machine model (mm); note 3 - 200 +200 v i lu(prot) latch-up protection current t amb = 125 c; v dd = 3.6 v - 200 ma i sc(dac) short-circuit current of dac t amb =0 c; v dd = 3 v; note 4 output short-circuited to v ssa(dac) - 20 ma output short-circuited to v dda(dac) - 100 ma symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 85 k/w symbol parameter conditions min. typ. max. unit supplies; note 1 v dda analog supply voltage 2.7 3.0 3.6 v v dda(dac) analog supply voltage for dac 2.7 3.0 3.6 v v dda(pll) analog supply voltage for pll 2.7 3.0 3.6 v v ddd digital supply voltage 2.7 3.0 3.6 v v ddd(c) digital supply voltage for core 2.7 3.0 3.6 v i dda(dac) analog supply current of dac power-on - 3.3 - ma power-down; clock off - 35 -m a i dda(pll) analog supply current of pll at f s =48khz - 0.5 - ma i ddd(c) digital supply current of core at f s =48khz - 9 - ma i ddd digital supply current at f s =48khz - 0.6 - ma p 48 power consumption at f s =48khz dac in playback mode - 40 - mw dac in power-down mode - tbf - mw
2003 mar 25 52 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl notes 1. all supply pins v dd and v ss must be connected to the same external power supply unit. 2. when the dac must drive a higher capacitive load (above 50 pf), a series resistor of 100 w must be used to prevent oscillations in the output stage of the operational amplifier. 3. the output voltage of the dac is proportional to the dac power supply voltage. digital inputs v ih high-level input voltage 0.8v ddd - v ddd + 0.5 v v il low-level input voltage - 0.5 - +0.2v ddd v ? i li ? input leakage current -- 10 m a c i input capacitance -- 10 pf r pu(int) internal pull-up resistance 16 33 78 k w r pd(int) internal pull-down resistance 16 33 78 k w digital outputs v oh high-level output voltage i oh = - 2 ma 0.85v ddd -- v v ol low-level output voltage i ol =2ma -- 0.4 v i o(max) maximum output current - 3 - ma digital-to-analog converter; note 2 v o(rms) output voltage (rms value) f i = 1.0 khz tone at 0 dbfs; note 3 850 900 950 mv d v o unbalance of output voltages f i = 1.0 khz tone - 0.1 0.4 db v ref reference voltage measured with respect to v ssa 0.45v dda 0.50v dda 0.55v dda v (thd+n)/s total harmonic distortion-plus-noise to signal ratio f i = 1.0 khz tone at f s = 48 khz at 0 dbfs -- 82 - 77 db at - 40 dbfs; a-weighted -- 60 - 52 db s/n 48 signal-to-noise ratio at f s =48khz f i = 1.0 khz tone; code = 0; a-weighted 95 100 - db a cs channel separation f i = 1.0 khz tone - 110 - db spdif inputs v i(p-p) ac input voltage (peak-to-peak value) 0.2 0.5 3.3 v r i input resistance - 6 - k w v hys hysteresis voltage - 40 - mv crystal oscillator f xtal crystal frequency - 12.288 - mhz c l load capacitance - 22 - pf symbol parameter conditions min. typ. max. unit
2003 mar 25 53 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 16 timing characteristics v ddd =v dda = 2.4 to 3.6 v; t amb = - 40 to +85 c; r l =5k w ; all voltages measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit device reset t rst reset active time - 250 -m s pll lock time t lock time-to-lock f s = 32.0 khz - 85.0 - ms f s = 44.1 khz - 63.0 - ms f s = 48.0 khz - 60.0 - ms serial interface input/output data timing (see fig.17) f bcki i 2 s-bus bit clock input frequency 1 t cy(bcki) ; note 1 -- 128f s hz f bcko i 2 s-bus bit clock output frequency 1 t cy(bcko) ; note 1 64f s 64f s 64f s hz t bckh bit clock high time 30 -- ns t bckl bit clock low time 30 -- ns t r rise time -- 20 ns t f fall time -- 20 ns t su(ws) word select set-up time 10 -- ns t h(ws) word select hold time 10 -- ns t su(datai) data input set-up time 10 -- ns t h(datai) data input hold time 10 -- ns t h(datao) data output hold time 0 -- ns t d(datao-bck) data output to bit clock delay -- 30 ns t d(datao-ws) data output to word select delay -- 30 ns l3-bus microcontroller interface (see figs 18 and 19) t cy(clk)(l3) l3clock cycle time 500 - ns t clk(l3)h l3clock high time 250 - ns t clk(l3)l l3clock low time 250 - ns t su(l3)a l3mode set-up time in address mode 190 - ns t h(l3)a l3mode hold time in address mode 190 - ns t su(l3)d l3mode set-up time in data transfer mode 190 - ns t h(l3)d l3mode hold time in data transfer mode 190 - ns t (stp)(l3) l3mode stop time in data transfer mode 190 - ns t su(l3)da l3data set-up time in address and data transfer mode 190 - ns t h(l3)da l3data hold time in address and data transfer mode 30 - ns t d(l3)d l3data delay time in data transfer mode 0 - 50 ns t dis(l3)r l3data disable time for read data 0 - 50 ns
2003 mar 25 54 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl notes 1. t cy(bck) is the bit cycle time. 2. c b is the total capacitance of one bus line in pf. i 2 c-bus interface timing; see fig.20 f scl scl clock frequency 0 - 400 khz t low scl low time 1.3 --m s t high scl high time 0.6 --m s t r rise time sda and scl note 2 20 + 0.1c b - 300 ns t f fall time sda and scl note 2 20 + 0.1c b - 300 ns t hd;sta hold time start condition - 0.6 --m s t su;sta set-up time repeated start condition - 0.6 --m s t su;sto set-up time stop condition - 0.6 --m s t buf bus free time between a stop and start condition - 1.3 --m s t su;dat data set-up time - 100 -- ns t hd;dat data hold time - 0 --m s t sp pulse width of spikes to be suppressed by the input ?lter - 0 - 50 ns c l(bus) capacitive load for each bus line --- 400 pf symbol parameter conditions min. typ. max. unit handbook, full pagewidth mgs756 ws bck datao datai t f t r t h(ws) t su(ws) t bckh t bckl t cy(bck) t h(datao) t su(datai) t h(datai) t d(datao-bck) t d(datao-ws) fig.17 serial interface input/output data timing.
2003 mar 25 55 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl handbook, full pagewidth t h(l3)a t h(l3)da t su(l3)da t cy(clk)(l3) bit 0 l3mode l3clock l3data bit 7 mgl723 t clk(l3)h t clk(l3)l t su(l3)a t su(l3)a t h(l3)a fig.18 timing for address mode. handbook, full pagewidth t stp(l3) t su(l3)d t h(l3)da t su(l3)da t h(l3)d t cy(clk)l3 bit 0 l3mode l3clock l3data read l3data write bit 7 mbl566 t clk(l3)h t clk(l3)l t d(l3)r t dis(l3)r fig.19 timing for data transfer mode.
2003 mar 25 56 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl handbook, full pagewidth msc610 s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta fig.20 timing of the i 2 c-bus transfer.
2003 mar 25 57 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 17 application information handbook, full pagewidth mgu613 uda1352hl 24 47 voutr 42 33 37 right_out r48 1 k w v8 hlmp-1385 (5x) j32 v ddd 0 1 2 3 j15 j17 v ddd 1 0 1 1 j14 v ddd l3-bus or i 2 c-bus static 2 3 1 2 3 v ddd i 2 c-bus l3-bus 1 2 3 j33 v ddd rst norm 1 2 3 45 r49 1 k w v9 23 r39 1 k w v5 31 r40 1 k w v6 43 r47 1 k w v7 pcmdet 9 wsi 8 bcki 7 datai 40 wso 36 bcko 48 18 27 n.c. n.c. n.c. 30 41 29 n.c. n.c. 11 1 39 datao userbit lock da0 seliic 38 selstatic 22 j31 j30 v ddd spdif i 2 s-bus 2 3 1 v ddd spdif i 2 s-bus 1 2 3 selspdif 21 selclk 14 j29 j28 v ddd no mute mute 2 3 1 v ddd spdif1 spdif0 1 2 3 selchan 13 mute da1 preem0 preem1 c16 47 m f (16 v) x19 x14 r45 10 k w r46 100 w 20 26 voutl vref left_out c15 47 m f (16 v) x18 x13 r43 10 k w r44 100 w l29 blm31a601s v dda(daca) reset v ssa(daca) v dda c43 100 nf (50 v) c14 100 m f (16 v) 25 35 34 test c44 100 nf (50 v) c13 10 m f (16 v) c3 100 m f (16 v) c5 100 m f (16 v) l30 blm31a601s c47 100 nf (50 v) c49 180 pf (50 v) c46 10 nf (50 v) c36 c35 b1 12.288 mhz c17 100 m f (16 v) r42 75 w x17 x12 v dda v dda(daco) 19 v ssa(daco) 28 v ssd 3 v ssd(c) v ddd(c) 4 v ddd v dda v ddd v ddd(e) 46 xtalin 15 xtalout 12 l27 blm31a601s c38 100 nf (50 v) c9 100 m f (16 v) v ddd 2 spdif1 17 l28 blm31a601s c42 100 nf (50 v) c12 100 m f (16 v) v dda c48 180 pf (50 v) c45 10 nf (50 v) r41 75 w x11 x16 spdif0 16 x10 x9 v dda(pll) v ssa(pll) c41 100 nf (50 v) c11 100 m f (16 v) v ddd(e) + 3 v gnd r1 1 w l3clock 6 clkout 32 oscout 44 l3mode 10 l3data 5 fig.21 application diagram.
2003 mar 25 58 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 18 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
2003 mar 25 59 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 19 soldering 19.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 19.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 19.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 mar 25 60 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 19.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2003 mar 25 61 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 20 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 21 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 mar 25 62 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl 23 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2003 mar 25 63 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352hl notes
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753503/02/pp 64 date of release: 2003 mar 25 document order number: 9397 750 10619

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